The present invention relates to circuits for decompressing image sequences, coded according to an MPEG standard and intended for being provided to a display circuit, and more specifically to an integrated circuit enabling displaying on a screen images incrusted in main images.
The MPEG coding standard enables storing the images of a digital image sequence in a reduced memory space. The MPEG coding provides digitizing the images of a sequence according to three categories. The beginning and end images of the sequences are coded independently and are called the xe2x80x9cintraxe2x80x9d images. A number of intermediary images, called xe2x80x9cpredictedxe2x80x9d images, are coded by taking account of their difference with the preceding intra or predicted image. The other images, called xe2x80x9cbidirectionalxe2x80x9d images, are coded by taking account of the intra or predicted images surrounding them. At the decoder level, coded image sequences are stored in a first memory and two successive decoded intra/predicted images are stored in a buffer. The first memory and the buffer usually are two areas of a same memory in which the MPEG decoder can read and write via a bus.
FIG. 1 very schematically shows an integrated circuit 2 that includes an MPEG decoder 4 connected to a bidirectional bus 8 by a coded data input CDI, a decoded data input DDI, and a decoded data output DDO. A memory 6 is also connected to be able to read or write on bus 8, and a display circuit 10 is connected to read on bus 8.
The function of decoder 4 is to decode coded images stored in memory 6. The decoder must, to decode certain images, use two previously-decoded images (intra/predicted). These two images are stored in memory 6 after their decoding by decoder 4. On the other hand, an image decoded by decoder 4 is not read immediately by display circuit 10, but is temporarily stored in memory 6. Thus, memory 6 must be able to contain, in addition to the coded images, three decoded images. Display circuit 10 displays each decoded image by reading it row by row from memory 6. The data read row by row are especially filtered and synchronized to be directly displayable, for example, by a television screen.
Many analog television sets provide, in addition to the display of a main image, the display of a sub-image, or incrusted image, on a fraction of the screen. It is also desired, in digital television, to make a circuit for decoding image sequences coded according to standard MPEG, which enables simultaneously displaying an incrusted image and a main image. An obvious solution would consist of duplicating circuit 2 to respectively decode and display the main images and the images to be incrusted. This solution would result in considerably increasing the cost of a television set, all the more as the circuit associated with the image to be incrusted will have to be even faster than the conventional circuit since the data associated with an image to be incrusted, of lower height than the normal height of an image, are of the same number as the data associated with a normal image but must be read in a fraction of the normal image scanning duration.
An embodiment of the present invention provides an electronic circuit that enables decoding and displaying a main image and an incrusted image while sharing the use of a single MPEG decoder and a single memory.
The circuit has limited memory size and memory reading speed requirements associated with the sharing of the memory.
The electronic circuit includes a memory connected to be accessible in the read and write mode from a bidirectional bus, an MPEG decoder having a coded image data input and a decoded image data input, the decoded image data corresponding to pixel sequences and the decoder inputs being connected to the bus to be able to read from the memory, and having a decoded image data output connected to the bus according to a first path to be able to write into the memory data of a first image, and a first image display circuit, an input of which is connected to said bus to be able to read from the memory the data written by the decoder, which further includes:
a digital filter providing one pixel among any sequence of a predetermined number of pixels, connected between the decoder output and said bus according to a second path to be able to write into the memory data of a second image, and a second image display circuit, an input of which is connected to the bus to be able to read from the memory the data written by the filter.
According to an embodiment of the present invention, the electronic circuit also includes a compression circuit connected in the first path, a first decompression circuit connected between the bus and the decoded data input of the decoder, and a second decompression circuit, followed by a block-to-row conversion circuit, connected between the bus and the first display circuit.